1. Field of the Invention
The present invention relates to register file circuitry for use, for example, in a processor or processor core. The present invention also relates to a register renaming method for use, for example, in pipelined loops in such a processor or processor core.
2. Description of the Related Art
In high performance computing, the requirement for cyclic register renaming arises in the context of software-pipelined loops, where a high rate of instruction execution is usually required of the target machine (e.g. microprocessor). Execution time is often dominated by loop structures within the application program. To permit a high rate of instruction execution a processor may include a plurality of individual execution units, with each individual unit being capable of executing one or more instructions in parallel with the execution of instructions by the other execution units.
Such a plurality of execution units can be used to provide a so-called software pipeline made up of a plurality of individual stages. Each software pipeline stage has no fixed physical correspondence to particular execution units. Rather, when a loop structure in an application program is compiled the machine instructions which make up an individual iteration of the loop are scheduled for execution by the different execution units in accordance with a software pipeline schedule. This schedule is divided up into successive stages and the instructions are scheduled in such a way as to permit a plurality of iterations to be carried out in overlapping manner by the different execution units with a selected loop initiation interval between the initiations of successive iterations. Thus, when a first stage of an iteration i terminates and that iteration enters a second stage, execution of the next iteration i+1 is initiated in a first stage of the iteration i+1. Thus, instructions in the first stage of iteration i+1 are executed in parallel with execution of instructions in the second stage of iteration i.
In such software-pipelined loops there are typically several iterations of a loop in a partial state of completion at each moment. Hence, there may be several live copies of each value computed within the loop. To distinguish between these values, and to identify them relative to the current iteration, requires that the name of each value held in a register must change at well-defined moments during loop execution. These renaming points are known by the compiler, which also determines the register name required within each instruction to access each value depending on the iteration in which it was computed.
The name of a value held in a register is known to the programmer or compiler in terms of the register identifiers within each assembly-code instruction. The purpose of static register renaming is to define a scheme whereby these identifiers are translated at runtime into actual register numbers based on a translation scheme that can be predicted by the programmer or compiler.
For example, if a value X is assigned to register r1 in iteration 1, a typical renaming scheme would make that value available in register r2 in iteration 2 and in register r3 in iteration 3, and so on. It is the responsibility of the compiler or programmer to allocate register identifiers to each value in a way that ensures correct operation of the loop.
In software pipelined loops there are usually loop-variant values, i.e. expressions which must be reevaluated in each different iteration of the loop, that must be communicated between different instructions in the pipeline. To deal with such loop-variant values it is possible to store them in a so-called rotating register file. In this case, each loop-variant value is assigned a logical register number within the rotating register file, and this logical register number does not change from one iteration to the next. Inside the rotating register file each logical register number is mapped to a physical register within the register file and this mapping is rotated each time a new iteration is begun, i.e. each time a pipeline boundary is closed. Accordingly, corresponding instructions in different iterations can all refer to the same logical register number, making the compiled instructions simple, whilst avoiding a value produced by one iteration from being overwritten by a subsequently-executed instruction of a different iteration.
With such a register renaming scheme in operation, before an instruction can be executed by the processor it is first necessary, for each register access within a software-pipelined loop, to perform a register mapping process to translate the register identifiers into actual register numbers. This mapping is done at run time and hence places extra time demands on the processor in a highly time-critical activity. It is therefore desirable that the time taken to perform this mapping is as small as possible.
Our co-pending United Kingdom patent application number 0004582.3 describes mapping circuitry capable of carrying out this mapping. That mapping circuitry receives as an input value a logical register number and produces an output value, within a preselected range of allowable values, representing an actual physical register number. The circuitry produces two candidate output values in parallel, the first candidate output value differing by a first offset value from the received input value, and the second candidate output value differing by a second offset value from the received input value. For any input value within a preselected range of allowable input values, one of the first and second candidate output values is within the preselected output-value range and the other of those two values is outside that range. The circuitry determines which one of the first and second candidate output values is within that preselected output-value range and selects that candidate output value as the final output value. The determination of the in-range candidate output value is also carried out in parallel with the production of the first and second candidate output values themselves. Although this mapping circuitry operates desirably fast in most practical applications, it is desirable to provide register file circuitry in which the mapping can be carried out even more quickly.
Register file circuitry according to the invention comprises a plurality of physical registers, and a plurality of tag storing portions corresponding respectively to the physical registers. Each tag storing portion stores a tag representing a logical register ID allocated to the corresponding physical register. A register selection unit receives a logical register ID and selects that one of the physical registers whose tag matches the received logical register ID.
In one aspect of the invention, a tag changing unit changes the stored tags by transferring the tag stored in at least one tag storing portion into another one of the tag storing portions. In this way a mapping between at least one logical register ID and one of the physical registers can be changed.
In another aspect of the invention the tag changing unit changes the stored tags so as to change a mapping between at least one logical register ID and one of the physical registers, and the circuitry has a physical register designating unit capable of designating at least one physical register of the plurality as a statically-named physical register whose tag is not changeable by the tag changing unit.
In another aspect of the present invention the register file circuitry comprises a plurality of tag management units corresponding respectively to the physical registers. Each tag management unit includes a tag storing portion for storing a tag representing a logical register ID allocated to the unit""s corresponding physical register. Each tag management unit can change the tag stored in the tag storing portion of its own unit. Two or more of the tag management units are operable in parallel with one another to bring about a change in mapping between at least one logical register ID and one of the physical registers.
In still another aspect of the present invention there is provided register file circuitry for use in a processor having a series of pipeline stages for executing instructions. This register file circuitry comprises a first plurality of tag storing portions, corresponding respectively to the physical registers and provided at a first one of the pipeline stages of the series. Each of these tag storing portions stores a working tag representing a logical register ID allocated to the corresponding physical register. The circuitry also comprises a second plurality of tag storing portions, corresponding respectively to the physical registers, for storing respective committed tags corresponding respectively to the working tags. A committed tag updating unit is connected to the second plurality of tag storing portions and updates the committed tags as instructions progress through the pipeline stages. A working tag reloading unit is connected to the first and second pluralities of tag storing portions. When a last valid instruction prior to occurrence of an exception has reached a last one of the pipeline stages, the working tag reloading unit reloads each working tag with its corresponding committed tag.
Register file circuitry as set out above can be provided in a processor.
Another aspect of the present invention can provide a register renaming method for use in register file circuitry having a plurality of physical registers. The method comprises storing tags in a plurality of tag storing portions corresponding respectively to the physical registers. Each stored tag represents a logical register ID allocated to the corresponding physical register. The stored tags are changed by transferring the tag stored in at least one tag storing portion into another one of said tag storing portions so as to change a mapping between at least one logical register ID and one of the physical registers.